Current artificial intelligent (AI) engines are usually designed for specific supervised learning algorithms, which have been widely used in computer vision and natural language processing domains etc. However, very few AI engines have been designed to support on-chip reinforcement learning algorithms, which is the foremost algorithm kernel for decision-making subsystem of many autonomous systems. In this work, a coarse-grained reconfigurable array like AI computing engine has been designed for the deployments of both supervised and reinforcement learning through on-chip configuration, action Random Access Memory (RAM) and reward RAM. Logic synthesis at the design frequency of 200 MHz based on 65 nm CMOS technology reveals the physical statistics of the proposed engine of 0.32 mm2 in silicon area, 15.46 mW in power consumption. The proposed on-chip AI engine facilitates the implementation of end-to-end perceptual and decision-making networks, which has great potentials in applications like autonomous driving, robotics and unmanned aerial vehicle.