Synthesis of Timed Admission Controllers
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    Abstract:

    In many real-time computing environments, there are some tasks that are time-critical while others are not. To ensure that every critical task can be completed before its deadline, it is necessary to reject some non-critical tasks to entry into the ready queue. We address this problem in the framework of controller synthesis. Our goal is to come up with an admission controller which admits or rejects a task request. With such a controller, no admitted tasks will miss their deadline and the admitted patterns of task releases satisfy a quality-of-service constraint in the form of a linear time temporal logic specification. We prove that it is decidable to determine if such an admission controller exists. Furthermore, if the answer is positive, it is possible to effectively construct a controller in the form of a finite timed controller.

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P. S. Thiagarajan, YANG Shaofa, WANG Yi. Synthesis of Timed Admission Controllers[J]. Journal of Integration Technology,2017,6(3):1-14

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  • Online: May 22,2017
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